Portable battery powered wireless communications devices, such as mobile terminals, cell phones, and the like, often have the ability to transmit information at different output power levels. When receive signal strengths are large, transmitting at lower output power levels can reduce battery consumption, decrease RF radiation exposure, and reduce RF interference. One way to reduce output power levels is to reduce operating voltages at the final stage of a transmitter power amplifier (PA) by using a DC-to-DC converter. DC-to-DC converters have requirements for printed circuit board (PCB) space, cost, and complexity, and may add the potential for spurious signals. An alternate architecture may be a multiple stage amplifier that bypasses certain stages for reduced output power; however, the required bypass circuitry can be somewhat complex. A more effective architecture may be a parallel amplifier circuit including a high power side and a low power side, which are both coupled to one RF output. By selecting the low power side for transmission at lower output power levels, efficiency can be maintained while using a relatively simple architecture.
One challenge of parallel amplifiers may be coupling the high power side to the low power side while preserving proper impedance matching for both sides. One technique is to provide separate impedance matching circuitry for each side and then isolate the two sides from each other using multiple one-quarter wavelength transmission lines on a PCB; however, space constraints may prohibit this technique. Another technique is to use a chain matching network coupled between the outputs of the two sides. One challenge of this technique is that a chain matching network may allow large voltage swings at the output of the low power side when the high power side is selected. These voltage swings may cause anomalous behavior in the low power side. Therefore, a need exists for a disabled power amplifier that can handle large voltage swings at its output.